Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Issue with compiling

Hi

I've run into a strange problem. I am using the schematic editor to create my design file, but when I go to compile, it gives me a few errors:

Warning: No paths found for timing analysis

Warning: Design contains 1 input pin(s) that do not drive logic

Warning (15610): No output dependent on input pin "SC"

Also, it says that no logic elements are being used after I compile.

The strange part is, when I have all the components not connected by wires, it appears to compile perfectly...

If anyone could help, that'd be great.

Thanks

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hello!

    It seems that Quartus has detected that your output isn't affected by any logic so it optimized your design (by removing all logic). Could you post some picture of your design so that we could try to identify the problem?

    Regards,

    Thiago
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Try assigning the PRN and CLRN DFF inputs to VCC. I think that if you leave them unconnected Quartus will automatically tie them to ground and the DFF will always be at reset.

    Regards

    Thiago