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Altera_Forum's avatar
Altera_Forum
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13 years ago

Issue when converting between multiple data types

Hello everybody I have an issue with this one line of code here: 


output(to_integer(unsigned(msbd) + unsigned(lsb)) downto 0) <= bit_field(to_integer(unsigned(msbd) + unsigned(lsb)) downto to_integer(lsb));

bit_field and output are 32 bit std_logic_vector

msbd and lsb are 5 bit std_logic_vectors

Issue is when I convert the VHDL file to a symbol file I get this: 


Error (10405): VHDL error at aluvhdl_entities.vhd(896): can't determine type of object at or near identifier "to_integer" -- found 0 possible types

Can some one tell me what the issue is?

28 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Im assuming lsb is a std_logic_vector? you forgot to cast it to an unsigned at the end of the line before using the to_integer conversion.

    PS. I dont think you'll get the circuit to synthesise if msbd and lsb are signals.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    use ieee.numeric_std.all;

    --- Quote End ---

    The thing is that I am using IEEE.NUMERIC_STD.ALL

    EDIT: I casted the std_logic_vector to unsigned and then integer. It created a bsf but now I will test synthesis

    EDIT2: I got this error during synthesis 

    
Error (10779): VHDL error at ALUVHDL_entities.vhd(896): expression is not constant
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    as I suggested - you cannot do this if msbd or lsb are signals and not constants.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    as I suggested - you cannot do this if msbd or lsb are signals and not constants.

    --- Quote End ---

    Is there any way how to circumvent that without resorting to a different design?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Yes - you'll need to use a for loop to check to see if each individual bit should be assigned,.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Then will I just need to use one for loop or will I possibly require more?

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start --- 

    
output(to_integer(unsigned(msbd) + unsigned(lsb)) downto 0) <= bit_field(to_integer(unsigned(msbd) + unsigned(lsb)) downto to_integer(lsb));

    bit_field and output are 32 bit std_logic_vector

    msbd and lsb are 5 bit std_logic_vectors

    --- Quote End ---

    Basically you are trying to do this:
     LHS(msb + lsb downto 0) <= RHS(msb + lsb downto lsb) ;
    which doesn't work as the LHS is wider than the RHS.

    Using for-loop won't work either as a for-loop needs constant boundaries as well.

    You could use a barrel shifter to dynamically align data.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    Basically you are trying to do this:
     LHS(msb + lsb downto 0) <= RHS(msb + lsb downto lsb) ;
    which doesn't work as the LHS is wider than the RHS.

    Using for-loop won't work either as a for-loop needs constant boundaries as well.

    You could use a barrel shifter to dynamically align data.

    --- Quote End ---

    Could it work if I pad the zeros in the beginning and the end?

    EDIT: I figured out that having two shifters will do it.