Is this a bug or just me with Quartus detecting the clock in an always_block.

Hello,

I have the following code and the following error when trying to compile in Quartus Prime. Line 72 refers to line 4 of the code snippet. And line 75 refers to line 7 of the code snippet.

Critical Warning (10237): Verilog HDL warning at xxx.sv(72): can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead
Critical Warning (10237): Verilog HDL warning at xxx.sv(75): can't infer register for assignment in edge-triggered always construct because the clock isn't obvious. Generated combinational logic instead

logic [AVALON_BUS_WIDTH - 1 : 0] read_write_combined [NUM_TOTAL_REG - 1: 0]; 
always_ff @ (posedge csi_clk or negedge rsi_n) begin
    if (!rsi_n) begin
        read_write_combined                         <= '{default:'0}; 
    end
    else begin
        for (int i = 0; i < NUM_CONTROL_REG; i++) begin
            read_write_combined[i]                   <= coe_control_reg  [((AVALON_BUS_WIDTH)*(i)) +: AVALON_BUS_WIDTH];
        end   
        for (int i = 0; i < NUM_STATUS_REG; i++ ) begin
            read_write_combined[i + NUM_CONTROL_REG] <= coe_status_reg   [((AVALON_BUS_WIDTH)*(i)) +: AVALON_BUS_WIDTH];  
        end
    end
end

My question is why is this error being thrown? I have other constructs that look very similar are not throwing this error. Reset is the very first thing in the always block, followed by an else statement with the rest of the code. Clock isn't mentioned at all.

Also, how can I fix this?

Thank you,

Tucker Z