Is there a way to encrypt design under Quartus?

Hi Daniel,

Thank you for your reply. My intent is *just* let my co-workers simulate my design(via Quartus, not FPGA board) without knowing the exact source code inside, so that they could know my design fulfill the requirements. I am actually looking for something that is exact the same as *.exe* file in C. So I think maybe QXP is what I want.

Ok, your intent is clear now. As you have mentioned in your own post, the way to let your co-worker verify your design without having a board is to simulate it. Quartus has removed (for good) its classic simulator, and has been shipping with ModelSim for a few years now.

So, exporting QXP to your co-workers mean they have to import it in Quartus, but that's usually to compile the design and generate a bitstream (.sof) which they can test on a board. I'm not so sure if they can generate a simulation netlist from a QXP, perhaps its possible, but I've not tried it.

One thing you can do is use the NativeLink feature of Quartus (or EDA Netlist Writer - maybe its also part of NativeLink) to generate netlists for 3rd-party tools, such as Mentor's ModelSim, Cadence's IES, etc. So, your co-worker can just take this netlist and simulate it with their simulator to verify its functionality without really testing it on a board.

The netlist isn't encrypted, but I think it's still obfuscated enough for your co-worker to quit trying to find out the original RTL behaviour just by reading your netlist. You can actually open up the netlist and read it to see if it's OK to give that netlist to your co-worker.

Netlist encryption is what Altera did for Verilog a few years ago (this is what many 3rd-party IP vendors use now), but unfortunately, VHDL-2008's IP encryption is not yet supported by Quartus (as far as I know). Anyone from Altera listening?

-daniel

"I am actually looking for something that is exact the same as *.exe* file in C."

You should start shifting your brain a little bit to move away from SW engineering principles to hardware principles. But anyway, as a _bad_ analogy, the closest equivalent of an .exe file is the bitstream binary file (.sof) which you download into your FPGA. This is the final assembled RTL design that you use to configure your FPGA.

Think of yourself as a chip designer now, rather than a software designer. You're really designing hardware (VHDL is hardware), with many concurrent processes (equivalent of threads in software). So your final compiled / assembled file is your hardware design file (which is the .sof) that you can use to configure the FPGA.

If you use a slightly different tool flow, say Mentor or Cadence, you will also write in VHDL / Verilog, but the final assembled design file is submitted to a foundry for chip fabrication. In fact, Altera uses this same ASIC design flow for its HardCopy series, where you can submit your final assembled netlist to Altera for them to fabricate a custom ASIC for you. Of course, the FPGA design flow is a simplified version of a full custom ASIC design flow.

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One thing you can do is use the NativeLink feature of Quartus (or EDA Netlist Writer - maybe its also part of NativeLink) to generate netlists for 3rd-party tools, such as Mentor's ModelSim, Cadence's IES, etc. So, your co-worker can just take this netlist and simulate it with their simulator to verify its functionality without really testing it on a board.

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Thank you, Daniel. I really appreciate it. Could you shed some light on how to use NativeLink to generate netlists for 3rd-party tools? Thanks.

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Could you shed some light on how to use NativeLink to generate netlists for 3rd-party tools? Thanks.

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I rather not post the steps here on how you can use NativeLink, as they are already been posted by Altera. Check out Altera's documentation (or online help) on NativeLink. First link on Google:

http://www.altera.com/support/examples/ncsim/exm-ncsim-native-link.html

This example is actually for ModelSim not ncSim like stated, but still it's pretty easy to use NativeLink with another simulator (e.g. ncsim or vcs) if you understand how to do it with ModelSim.

-daniel