Is there a way to encrypt design under Quartus?

"I am actually looking for something that is exact the same as *.exe* file in C."

You should start shifting your brain a little bit to move away from SW engineering principles to hardware principles. But anyway, as a _bad_ analogy, the closest equivalent of an .exe file is the bitstream binary file (.sof) which you download into your FPGA. This is the final assembled RTL design that you use to configure your FPGA.

Think of yourself as a chip designer now, rather than a software designer. You're really designing hardware (VHDL is hardware), with many concurrent processes (equivalent of threads in software). So your final compiled / assembled file is your hardware design file (which is the .sof) that you can use to configure the FPGA.

If you use a slightly different tool flow, say Mentor or Cadence, you will also write in VHDL / Verilog, but the final assembled design file is submitted to a foundry for chip fabrication. In fact, Altera uses this same ASIC design flow for its HardCopy series, where you can submit your final assembled netlist to Altera for them to fabricate a custom ASIC for you. Of course, the FPGA design flow is a simplified version of a full custom ASIC design flow.