Is there a way to encrypt design under Quartus?

Ok, your intent is clear now. As you have mentioned in your own post, the way to let your co-worker verify your design without having a board is to simulate it. Quartus has removed (for good) its classic simulator, and has been shipping with ModelSim for a few years now.

So, exporting QXP to your co-workers mean they have to import it in Quartus, but that's usually to compile the design and generate a bitstream (.sof) which they can test on a board. I'm not so sure if they can generate a simulation netlist from a QXP, perhaps its possible, but I've not tried it.

One thing you can do is use the NativeLink feature of Quartus (or EDA Netlist Writer - maybe its also part of NativeLink) to generate netlists for 3rd-party tools, such as Mentor's ModelSim, Cadence's IES, etc. So, your co-worker can just take this netlist and simulate it with their simulator to verify its functionality without really testing it on a board.

The netlist isn't encrypted, but I think it's still obfuscated enough for your co-worker to quit trying to find out the original RTL behaviour just by reading your netlist. You can actually open up the netlist and read it to see if it's OK to give that netlist to your co-worker.

Netlist encryption is what Altera did for Verilog a few years ago (this is what many 3rd-party IP vendors use now), but unfortunately, VHDL-2008's IP encryption is not yet supported by Quartus (as far as I know). Anyone from Altera listening?

-daniel