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Altera_Forum's avatar
Altera_Forum
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15 years ago

Is there a way to avoid symbol files to change ports positions?

Hi all

I have a VHDL block which has generated a symbol file I'm using on a schematic file.

Every time I edit the VHDL and add and/or remove interface signals, I have to update my symbol file. The problem is that the symbol generated does not keep previous signals positions in my symbol file, so I have to re-arrange signal positions in my schematic file every time I update the VHDL. Since my interface is getting bigger, it means a lot of work.

Is there a way to set symbol editor to keep positions when updating files?

Thanks in advance

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    After you edit your VHDL, you're regenerating your .bsf file, right? The .bsf is purely an output of that function, i.e. it's not read back in and compared with the changes. I think the only way is to not overwrite the .bsf and instead, when you make changes to your VHDL, directly edit the symbol to match that.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks Rysc

    I was just wondering if there was another way to do it, it seems there isn't.

    best regards
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    As far as I know, there is no other way, but if you don't want to edit your symbol every update, you can keep a few things in mind:

    - All inputs are on the left, all ouputs are on the right.

    - The order of port declaration in VHDL will be the order of the ports in the symbol, top down.

    So if you only add ports in VHDL after the ones you already have, the upper part of the symbol remains the same and the symbol grows down.

    Don't remove ports in VHDL even they are not connected any more. This way other ports won't shift one position up. Give them another name like "NC1", "NC2" or so.

    I admitt this makes your VHDL and symbol less readable, but at least you don't have to edit your symbol every update.

    Good luck, Ton
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Or just dont use the graphical editor at all and instantiate everything in VHDL.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    Or just dont use the graphical editor at all and instantiate everything in VHDL.

    --- Quote End ---

    Tricky, you're right.

    But although I use VHDL for almost 20 years, I prefer to use schematics for my toplevel. I miss the overview in structural VHDL.

    -- Ton