Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Is there a way to avoid symbol files to change ports positions?

Hi all I have a VHDL block which has generated a symbol file I'm using on a schematic file. Every time I edit the VHDL and add and/or remove interface signals, I have to update my symbol fil...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

As far as I know, there is no other way, but if you don't want to edit your symbol every update, you can keep a few things in mind:

- All inputs are on the left, all ouputs are on the right.

- The order of port declaration in VHDL will be the order of the ports in the symbol, top down.

So if you only add ports in VHDL after the ones you already have, the upper part of the symbol remains the same and the symbol grows down.

Don't remove ports in VHDL even they are not connected any more. This way other ports won't shift one position up. Give them another name like "NC1", "NC2" or so.

I admitt this makes your VHDL and symbol less readable, but at least you don't have to edit your symbol every update.

Good luck, Ton