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Altera_Forum's avatar
Altera_Forum
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15 years ago

Is there a way to avoid symbol files to change ports positions?

Hi all I have a VHDL block which has generated a symbol file I'm using on a schematic file. Every time I edit the VHDL and add and/or remove interface signals, I have to update my symbol fil...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Or just dont use the graphical editor at all and instantiate everything in VHDL.

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Tricky, you're right.

But although I use VHDL for almost 20 years, I prefer to use schematics for my toplevel. I miss the overview in structural VHDL.

-- Ton