Forum Discussion
Altera_Forum
Honored Contributor
12 years agoNot so much a problem, as the processor model works fine as it stands. I have shipping designs running with it at 66MHz with margin to spare. I am looking at doing some newer designs where I would like to target 100MHz, though, and I was having trouble meeting that with the current model. Assuming no more bugs show up in regression testing, my new model is hitting 112MHz in the same design. The critical path is now largely between the address bus and the ROM, though there are still some low margin figures in the ALU core; but since I'm making timing, I'm not sure it's worth the pain of continuing to optimize the model.
My biggest issue now is deciding how badly the increased instruction latency is going to cost me. Math operations that used to stream through in a single clock cycle are now taking three clock cycles to complete because I am having to back up the program counter to account for the additional clock cycle in the ALU path. I just wanted to make sure I wasn't throwing anything away by using variables in a single clocked process instead of the more traditional signals between a clocked and combinatorial process.