Forum Discussion
In this case, I actually want combinatorial logic,not registers. IOW, I need the logic that is set by these variables to complete on the current clock, so the variables are being used the same way signals between processes were being used in the older model. (I actually have gone to a great deal of trouble to make sure that none of these variables inadvertently imply a flip-flop.) The variables were simply to help with maintainability, so that rather than have to actually copy the bits of code into each state where they are used, the code is written once and effectively "called" from the states where they are used. IOW, I could have just as easily written it so that every time I need to prefetch the next instruction, I just do a CPU.Prefetch <= Rd_Data; instead.
I believe it should produce identical netlists, but I know that sometimes the synthesizer can have issues with certain code models. The question had more to do with how Quartus treats variables used in this manner, so I may have posted in the wrong area.