Is there a Bug about the Quartus II?

In your Verilog test bench the eachvec signal is declared but not used.

This creates an unknown signal.

Your process does not have a $stop; instruction at the end.

This keeps Modelsim simulating for very long time and can cause problems.

Without these small errors the simulation, both RTL and Gate Level proceeds without problems.

Further, I've never seen the use of negedge or posedge that you show in order to syncronize the test vectors with the clock.

However, it seems to work

Hope this helps.