Is the speed determined by fmax or delays?

To further add to my post about fmax anatomy:

Fmax is dependant on register Tsetup and reg to reg delay.

--------x--------------x------- launching clk edge

----------x--------------x ------------ launched data transitions

dd--------x---------------x------- latching clk edge

dd----------x---------------x ------------ arrived data transitions

.................AAAAAAAAASSHH...................S is setup window

the arriving data transition has the interval window AAAA.. else it will violate setup at S.

this window = clk period - SS -reg Tco(which is intrinsic)

Remeber f = 1/clk period

The AAAA.. interval is normaly not through direct wire but a comb. section. Thus you can break it up shorter to approach maximum posiible speed for the given device which then is limited by intrinsic reg tco and reg quality...

arrival of data beyond at HHH violates hold time. this is due in practice to clk arriving late and is tackled by internal design to ensure fast clk tree.

I said in practice because it might well occur due to excessive data delay but at such point fmax is already violated and so hold violation drops from discussion.