Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Is Quartus capacitive loading setting add real capacitance to FPGA pins?

The setting locates in Quartus [Assignments]-->[Settings]-->[Device]-->[Device and Pin Options]-->[Capacitive Loading tab]. At first I took it as only a value specified for timing analysis, but latel...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The capacitive load setting you provide in Quartus is for *you* to tell Quartus what is physically connected to the FPGA/CPLD I/O pins. For example, if you have a Flash or SRAM device connected to an I/O pin, and the data sheet for that device indicates 10pF per device pin, then you use that value in the capacitive load setting in Quartus. This allows Quartus and TimeQuest to adjust the clock-to-output timing for the additional capacitance on the pin. The TimeQuest results (margins) are then more realistic.

Quartus already knows about the pin capacitance of the FPGA/CPLD package, and the "extra" internal capacitance on the VREF pins. You can see this in a TimeQuest report as the clock-to-output delay for the VREF pins is larger (so do not use them for high-speed signals).

Cheers,

Dave