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jorva's avatar
jorva
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Is it possible to archive snapshots?

Hello,

I would like to be able to archive Quartus Pro's intermediate results in a similar manner that Vivado does with design checkpoints (.dcp). The snapshot seemed to be a similar tool but, on further investigation, doesn't seem to be geared towards this kind of usage.

For example, even though I activated the creation of the snapshots (and they are available when opening the project), I cannot export to a .qdb file (error message: 'no partitions are available to export'). Why can't the default partition be exported?

The objective is to be able to go back to some previous implementation results (of a complete design) without having to rerun the complete implementation.

Thanks for your help!

20 Replies

  • ADM123's avatar
    ADM123
    Icon for New Contributor rankNew Contributor
    4 years ago

    To archive a snapshot:

    1. Select the Process Apps or Toolkits tab.
    2. Select the process application or toolkit for which you want to archive snapshots. If multiple tracks exist, select the track that you want from the drop-down menu.
    3. Find the snapshot that you want, and then click Archive from its pop-up menu ().
    4. When prompted, click Archive to confirm your selection.
  • ADM123's avatar
    ADM123
    Icon for New Contributor rankNew Contributor
    4 years ago

    To archive a snapshot:

    1. Select the Process Apps or Toolkits tab.
    2. Select the process application or toolkit for which you want to archive snapshots. If multiple tracks exist, select the track that you want from the drop-down menu.
    3. Find the snapshot that you want, and then click Archive from its pop-up menu ().
    4. When prompted, click Archive to confirm your selection.
  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    I'm not sure what the previous poster is referring to, but there is supposed to be an option (Project menu -> Export Design) as opposed to (Project menu -> Export Design Partition). The export design option is supposed to let you export the synthesized or final design as a whole as a .qdb (page 46 here: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-compiler.pdf). For some reason, I'm not seeing that option in 20.4 even though it is documented in the user guide. Hmm.

    What you could do if you are not partitioning your design is to export the whole design as a partition (referred to as the root_partition in the tool). Open the Design Partitions window from the Assignments menu and click the 3 dots (...) to add the "Post Synthesis Export File" and "Post Final Export File" options. Enter .qdb file names in these columns for the root_partition, and that will automatically create post synthesis and final .qdb files for the entire design.

    I'm not sure if this is what you are looking for.

    • jorva's avatar
      jorva
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      Hello @sstrell,

      (Project menu -> Export Design) doesn't exist in the version I'm using either (QPro 20.2).

      I believe your second suggestion is what I'm looking for and I tried it through scripting (in the Quartus tcl console):

      load_package design
design::export_partition root_partition -snapshot synthesized -file ip.qdb
Error:0x1a3be630
Error:    while executing
Error:"design::export_partition root_partition -snapshot synthesized -file post_synth.qdb"

      However, I haven't tested yet with the qsf assignments:

      set_instance_assignment -name EXPORT_PARTITION_SNAPSHOT_SYNTHESIZED post_synth.qdb -to | -entity top_fpga_ddr4
set_instance_assignment -name EXPORT_PARTITION_SNAPSHOT_FINAL post_fit.qdb -to | -entity top_fpga_ddr4

      This requires a re-run of the implementation I guess? That takes some time...

      • jorva's avatar
        jorva
        Icon for Occasional Contributor rankOccasional Contributor
        4 years ago

        Just saw the following explanation for the error:

        Error(18895): The TCL command design::export_partition from the design package is not supported while running on the Quartus Graphical User Interface

        The idea is to do it using scripting anyways so I'll try that.

    • jorva's avatar
      jorva
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      @KennyTan_Altera Thanks for the suggestion.

      I tried to follow "1.5.2. Reusing Root Partitions". However, I don't do the steps described in 1.5.2.1 and 1.5.2.2 as my objective is not to create a root_partition with the peripherals and a reserved space for future use (see my previous post). As per 1.5.2.3 the fitter completes but then I get the same error as in my initial post when I try the second step: 'No partitions are available for export.'

  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Did your .vhdl/v consist of peripheral code like DDR/PCIE/Tranceiver?

    Can you attached your design.qar files us to take a look?


    Thanks,



    • jorva's avatar
      jorva
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      @KennyTan_Altera Sorry for the delay.

      The design does include DDR. These are proprietary files which I cannot share in this forum.

  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    It would be abit hard without looking into the design.qar files.


    Can you check your email? we will discuss more on there.


  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    I try to compile the design in Q20.4 pro.

    I am getting error:

    Error(13785): VHDL Use Clause error at BurstGenWr.large_design.vhd(61): design library "altera_work" does not contain primary unit "toolspck"

    Error(13786): VHDL error at BurstGenWr.large_design.vhd(151): object "log2" is used but not declared

    Error(13786): VHDL error at BurstGenWr.large_design.vhd(155): object "log2" is used but not declared


    Is there any things missing in the Qar files?


  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Sorry, I will need sometime to work on this. Will get back to you by end of next week.


  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    can you try to use include at the top of your .v/vhdl files to include the necessary files?