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Altera_Forum's avatar
Altera_Forum
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11 years ago

is "for loop" in counter looping according clock cycle?

Hi, all I would like to create a adjustable delay counter using verilog. I use for loop inside. However, I notice that the for loop does not count base on clock cycle. Any mistake I done? Bel...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

for loops unroll into parrallel hardware. So you have receivesize different comparitors all trying to set abc to 1. In your case, the lowest value of receiveSize will always win, and so is always set to that.