Forum Discussion
IP-SDRAM/LPDDR2
- 3 years ago
Hi Suphachai,
I will share the protocol support matrix by Intel FPGA for UniPHY based families in the LINK: https://www.intel.com/content/www/us/en/docs/programmable/710283/17-0/protocol-support-matrix.html
You may check which devices can support LPDDR2 protocol.
For LPDDR2 IP, it's known as LPDDR2 SDRAM Controller with UniPHY Intel FPGA IP.
We have 3 EMIF handbooks for UniPHY based device families. These are the reference documents for LPDDR2 IP.
- Volume 1: https://www.intel.com/content/www/us/en/docs/programmable/710283/17-0/introduction-to-this-handbook.html
- Volume 2: https://www.intel.com/content/www/us/en/docs/programmable/683385/17-0/planning-pin-and-fpga-resources.html
- Volume 3: https://www.intel.com/content/www/us/en/docs/programmable/683841/17-0/functional-description-uniphy.html
Regards,
Adzim
Hi Suphachai,
I will share the protocol support matrix by Intel FPGA for UniPHY based families in the LINK: https://www.intel.com/content/www/us/en/docs/programmable/710283/17-0/protocol-support-matrix.html
You may check which devices can support LPDDR2 protocol.
For LPDDR2 IP, it's known as LPDDR2 SDRAM Controller with UniPHY Intel FPGA IP.
We have 3 EMIF handbooks for UniPHY based device families. These are the reference documents for LPDDR2 IP.
- Volume 1: https://www.intel.com/content/www/us/en/docs/programmable/710283/17-0/introduction-to-this-handbook.html
- Volume 2: https://www.intel.com/content/www/us/en/docs/programmable/683385/17-0/planning-pin-and-fpga-resources.html
- Volume 3: https://www.intel.com/content/www/us/en/docs/programmable/683841/17-0/functional-description-uniphy.html
Regards,
Adzim