IP lpm_ff has been removed?

If you want to implement sync and async reset this is easily done in Verilog:

module dFF(
   input clk,
   input asyncReset,
   input syncReset,
   input d,
   output q
);
   reg r;
   assign q = r;
   always @(posedge clk, posedge asyncReset) begin
      if(asyncReset)
         r <= 1'b0;
      else if(syncReset)
         r <= 1'b0;
      else
         r <= d;
   end
endmodule