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Yannick's avatar
Yannick
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5 years ago
Solved

IP catalogue different in Platform Designer

Hello everyone, I'm just getting started with FPGA programming and using a Cyclone V GT development kit with Quartus Prime Lite 18.1. To begin with, I followed a lot of the provided training and...
RichardT_altera's avatar
RichardT_altera
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5 years ago

Some Intel IP cores may or may not support the Qsys and SOPC Builder design flows and the Native Transceiver Native Phy Intel Cyclone V IP seems to be one of it that does not support the Qsys flow.

You may checkout a similar forum case. There's some broken link which I can't do much about it.

https://community.intel.com/t5/FPGA-Intellectual-Property/Cyclone-V-Transceiver-Native-PHY-IP-not-available-in-Qsys/td-p/234271?profile.language=en

Since you beginning to begin your design with this IP, you may also checkout the Cyclone V Transceiver PHY Basic Design. There are a few design examples that you can refer to:

https://community.intel.com/t5/FPGA-Wiki/Cyclone-V-Transceiver-PHY-Basic-Design-Examples/ta-p/735390

  • Yannick's avatar
    Yannick
    Icon for New Contributor rankNew Contributor
    5 years ago

    Thank you for the quick reaction and insight. I was searching more generally and didn't see the other entry.

    That should get me started.

    • RichardT_altera's avatar
      RichardT_altera
      Icon for Super Contributor rankSuper Contributor
      5 years ago

      I’m glad that your question has been addressed, I will now transition this thread to community support.

      If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.