IO_OBUF polarity not matching RTL

I made a very simple new project. The same device (AGFB014R24B2E3V). This is the RTL.

module tri_test (

input logic clk1,
input logic clk2,

input logic en1,
input logic en2,

output logic out1,
output logic out2
);

assign out1 = (en1) ? clk1 : 1'bz;
assign out2 = (en2) ? clk2 : 1'b0;

endmodule

You can see that out1 "should" be clk1 if en1 is high, and Hi-Z if en1 is low. You can also see the post-fit Technology Map Viewer shows the polarity implemented is wrong (there is no inverter added to compensate for the active-low OE on the IO_OBUF primitive).

The out2 circuit is the same logic, but without the tri-state (it just outputs 0 if en2 is low).

The whole project folder is now attached.