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Robert_H_Intel's avatar
Robert_H_Intel
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4 years ago

IO_OBUF polarity not matching RTL

I am working on a design using an Agilex F-series part (AGFB014R24B2E3V) and am having issues with tri-stated outputs. The RTL in question is: assign TRIG[0] = (lb_enable_dd) ? clk_fast : 1'bz; ...
Robert_H_Intel's avatar
Robert_H_Intel
Icon for New Contributor rankNew Contributor
4 years ago

The problem still persists. The Quartus synthesis is failing to add the required inverter in front of the IO_OBUF to match the logic in my RTL.

Inverting it on my end changes my intended logic (and would still likely be wrong on my end).

The issue appears to be in the tools, not my RTL, so I can't see a way that I can fix this on my end.

ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi Rob,

Can you provide a sample file which duplicates the issue for better viewing? If that's a bug, I can reflect this to internal team with the reference file.

Thanks,

Best regards,
Sheng