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Robert_H_Intel's avatar
Robert_H_Intel
Icon for New Contributor rankNew Contributor
4 years ago

IO_OBUF polarity not matching RTL

I am working on a design using an Agilex F-series part (AGFB014R24B2E3V) and am having issues with tri-stated outputs. The RTL in question is: assign TRIG[0] = (lb_enable_dd) ? clk_fast : 1'bz; ...
Robert_H_Intel's avatar
Robert_H_Intel
Icon for New Contributor rankNew Contributor
4 years ago

"So when using assign TRIG[0] = (lb_enable_dd) ? clk_fast : 1'bz;, an inverter is automatically added to make the RTL matches the IO_OBUF primitive"

You seem to be missing the point. The tools ARE NOT automatically adding this inverter, that is my whole issue!!!!!

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Hi Rob,

    What I mean is assign TRIG[0] = (lb_enable_dd) ? clk_fast : 1'bz; represents the whole IO_OBUF primitive. For that assign, obviously '1' is needed to trigger the clk_fast. However, IO_OBUF primitive needs to function as active low OE means lb_enable_dd needs to be '0' at any point. For that assign, if lb_enable_dd is '0' 1'bz will be selected right? If like that IO_OBUF is not active low OE anymore. So an inverter is automatically added to compensate for that (first pic you share).

    In order to use '1' for clk_fast triggering, you have to manually add a not gate or inverter.

    Best regards,
    Sheng