I/o Ff

Question

Hi,

I'm somewhat of a newbie with regard to the QuartusII tools, I just came over from Camp "X".

I'm having some trouble trying to infer the use of the register on the input pad (SIIGX), or even in trying to force Quartus to do so. I've even tried adding the synthesis directive /* synthesis useioff = 1 */ to the input ports in question. Is there possibly some compilation setting I've used that is overriding this directive? Could it possibly be the way I've constructed the synchronous statement?

Thanks.

altera_forum · Answer

In the Assignment Editor, create a setting on the pin (or input register) for Fast Input Register = ON.  (For output registers, set Fast Output Register = ON).  Another way to force the register into the input I/O cell is to use a very tight setup constraint.

altera_forum · Answer

If it still doesn't work with jimbo's suggestion, it might be that synthesis is creating a structure that can't use the register location in the I/O cell. I've seen something like synchronous load do this. This could happen because of what you coded in the HDL, and it could happen just because of a choice Analysis & Synthesis made that you can't control with the coding style. Fast Input Register is a Fitter setting, so Analysis & Synthesis doesn't know that it needs to implement something compatible with that Fitter setting.

You can look at the register equation at the bottom of the Chip Planner window when the register is selected or in an equations file produced by "Processing --> Start --> Start Equation Writer". Compare the control signal usage in the equation to what the Stratix II GX device handbook shows as available in the figure that has the I/O cell registers and control signals.

altera_forum · Answer

Acutally, your compiler directive should have worked.  I should have pointed out that this will only work if you have no logic before the FF, and that the register is not part of a carry chain.  Perhaps that's why your compiler directive didn't work?

altera_forum · Answer

If you prefer doing things in the source code (which I don't recommend in this particular instance) Quartus assignments can be done within the source code by using verilog attributes. So before the declaration of your signal you would add something like:

(* altera_attribute = "FAST_OUTPUT_REGISTER=ON" *)

Jake

altera_forum · Answer

Thanks for all the quick replies so far...

I'm giving jimbo's first suggestion a try, will see if it works out... Is Altera going to come out with "Instant Compilation" in Quartus9?:)

I was thinking that it may have been the way I setup my synchronous construct.

As it's still in the process of compiling, I still see that am getting the following warning:

warning (10890): verilog hdl attribute warning at dvi_input.v(17): overriding existing value for attribute "useioff"

(It took me a while to figure out how to add the Fast IO attribute and I didn't remove the 'useioff' from my port description, yet...)

Will let you know how things work out.

Thanks again.

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I/o Ff

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