Thanks for all the quick replies so far...
I'm giving jimbo's first suggestion a try, will see if it works out... Is Altera going to come out with "Instant Compilation" in Quartus9?:)
I was thinking that it may have been the way I setup my synchronous construct.
As it's still in the process of compiling, I still see that am getting the following warning:
warning (10890): verilog hdl attribute warning at dvi_input.v(17): overriding existing value for attribute "useioff" (It took me a while to figure out how to add the Fast IO attribute and I didn't remove the 'useioff' from my port description, yet...)
Will let you know how things work out.
Thanks again.