I/o Ff

If it still doesn't work with jimbo's suggestion, it might be that synthesis is creating a structure that can't use the register location in the I/O cell. I've seen something like synchronous load do this. This could happen because of what you coded in the HDL, and it could happen just because of a choice Analysis & Synthesis made that you can't control with the coding style. Fast Input Register is a Fitter setting, so Analysis & Synthesis doesn't know that it needs to implement something compatible with that Fitter setting.

You can look at the register equation at the bottom of the Chip Planner window when the register is selected or in an equations file produced by "Processing --> Start --> Start Equation Writer". Compare the control signal usage in the equation to what the Stratix II GX device handbook shows as available in the figure that has the I/O cell registers and control signals.