Intrroducing delay at pin level

A positive hold requirement is meant to introduce delays. (Ideally we want to design where the fitter doesn't have to do this, but I've seen enough examples that it is useful). And in reality, he'll have to put in Timing Constraints first to ever know if that 10ns requirement is being met. I have seen the router go halfway across the chip and then back again, just to add delays to two nodes right next to each other, so it does do more than IO delays or small adjustments of existing routes. I figure it's worth a shot, but agree there's a "niceness" to adding a physical delay chain made of LUTs.