Intrroducing delay at pin level

The requirement in the first post was 10 ns, and that's probably too much. I agree, that for smaller delays, one should try with timing constraints first.

The point is, that timing constraints never cause the compiler to add additional delay elements (except for using the rather small programmable I/O delay), they only cause a variation of the predefined routing. So the available range of timing adjustment depends on the routing delay that already exists in the design. It may be rather large for a complex, distributed design or small for a compact design.

In my understanding, the purpose of timing constraints is mainly to assure the correct design implementation considering logic element, I/O and routing delays. They are not intended to introduce arbitrary delays.