Intrroducing delay at pin level

I've seen some designs with pretty large hold requirements, whereby Quartus has properly added many nanoseconds of delay(don't remember the exact number, but I think it was around 5ns). Looking in the chip-editor, it was routed all over the place to connect to cells that were right next to each other. So it did a good job, and I wouldn't automatically assume that Quartus couldn't do it with timing constraints alone.