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Honored Contributor

17 years ago

Intrroducing delay at pin level

Hello All, I am new to the Quartus tool, I just need your help to solve my doubts. I wanted to that "How to introduce output delay at pin level" Example: I have two input signals in...

Altera_Forum

Honored Contributor

17 years ago

I don't think, that timing driven place and route will give a sufficient delay amount. You possibly have to use additional logic cells that are protected by a keep synthesis attribute.

See e. g. http://www.alteraforum.com/forum/showthread.php?t=2418

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Intrroducing delay at pin level

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