Intrroducing delay at pin level

Yes; I do agree with your answer. But In this case op1 and op2 are going to the buffer chip as enable and direction. Here the generation of the op1 and op2 shall be independent of clock. Its a requirement, so I cannot use the clock to do this. op1 is going as enable to the data buffer, op2 is going as direction to the data buffer. Now first i have to set the direction and then I have to give the enable. the delay between these shall be at least 5 ns.