Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Intrroducing delay at pin level

Hello All, I am new to the Quartus tool, I just need your help to solve my doubts. I wanted to that "How to introduce output delay at pin level" Example: I have two input signals in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I suggest you to use a synchronous approach to this problem. You should use a clock with period equal to the desired delay and use a simple VHDL block to produce the output after a clock edge.

The asynchronous solutions are always less reliable than the synchronous ones, so I don't recommend you to use them.