Forum Discussion
Altera_Forum
Honored Contributor
13 years agoCan I ask you, is it OK to assign the ports of top level entity as virtual pins except clock? I am doing this because the total number of pins required for the ports of the top level entity are much more than the Stratix IV device family. After this assignment is run the fitter which is successful but once I run the EDA Netlist Writer, after 25%, it gave me that error that I mentioned in the first post.