Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/vpr_common/place

Ahhh! I'm getting this error during the fitter register retiming step every time I compile!

I saw a post on Altera's KnowledgeBase regarding this error (http://www.altera.com/support/kdb/solutions/rd12222009_898.html); (http://www.altera.com/support/kdb/solutions/rd12222009_898.html%29;) I followed the advice but it didn't solve the problem.

Has anyone else had this error? My project compiled fine before I added LogicLock regions.

Tool: Quartus II 9.1 SP1

Chip: Stratix IV GX

General config: 32 rectangular LogicLock regions, each with a child region.

Info: Starting physical synthesis algorithm register retiming
Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/vpr_common/place_constraints.c, Line: 1698
Internal Error
Stack Trace:
     0x2034: FSYN_ENV::vpr_qi_do_timing_analysis_and_incremental_placement_for_fsyn + 0x34 (fitter_fsyn)
     0x6429: CSYN_EXPERT::operator= + 0x4749 (DB_CSYN)
    0x44b9a: CSYN_EXPERT::run_single_algorithm + 0x2ba (DB_CSYN)
    0x4c8d0: CSYN_EXPERT::is_atom_modified_for_icp + 0x7b20 (DB_CSYN)
    0x43c18: CSYN_EXPERT::run_flow + 0xe8 (DB_CSYN)
    0x42631: CSYN_EXPERT::run_fsyn_user_option_flow + 0x221 (DB_CSYN)
    0x4320f: CSYN_EXPERT::late_fsyn_flow + 0x18f (DB_CSYN)
    0x432cc: CSYN_EXPERT::late_fsyn_flow + 0x24c (DB_CSYN)
   0x1429d4: CSYN_SAVE_RESTORE_MGR::get_number_of_snapshots + 0x101c4 (DB_CSYN)
   0x13d54e: CSYN_SAVE_RESTORE_MGR::get_number_of_snapshots + 0xad3e (DB_CSYN)
    0x40f35: CSYN_EXPERT::do_physical_synthesis + 0x5c5 (DB_CSYN)
     0x9702: MEM_SEGMENT_INTERNAL::locked_allocate + 0x62 (ccl_mem)
     0xa268: mem_realloc_wrapper + 0x188 (ccl_mem)
     0x1cac: mem_delete_wrapper + 0x2c (ccl_mem)
    0x101df: DYGR_DIE_INFO_BODY::matches_pin_table_version + 0xcf (DDB_DYGR)
     0xe199: FITAPI_FSYN::do_physical_synthesis + 0x59 (fitter_FITAPI)
End-trace