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Honored Contributor
Honored ContributorInternal Error : Expected to get 1 pll but found 3 plls for group EMIF_0_mem_ctrl_alt
My design contains several PLL's : - a PLL to generate the main system clock. - a PLL for the DDR controller. - a PLL in a PCIe interface IP. Recently my builds have been crashing with a...
Altera_ForumHonored Contributor
Honored ContributorHi,
Probably you have a DDR interface that more than 40bits data width? The duplicate PLL is expected because the EMIF use 3 I/O banks. For EMIF once the EMIF is place into the particular bank, it will use that bank I/O PLL to generate clocks for the I/O banks DDR signals. you may refer to EMIF handbook https://www.altera.com/documentation/hco1416493470528.html#hco1416492698401 Arria 10 EMIF Architecture: PHY Clock Tree section Arria 10 EMIF Architecture: PLL Reference Clock Networks section (This message was posted on behalf of Intel Corporation)