Interfacing Controller for SDR SDRAM Memory with FPGA Centric Approach

I think I was not clear.

The pll performs the 180 degree shift, so the clock and data coming to the memory are center-aligned.

But for the input side, the input clock doesn't come from the memory but from the oscillator ( input H ) which is not shifted. If I perform a read command to the SDRAM, we can say that the data changes on the edge of H_sdram.

So is it possible that the data and the main clock are "automatically" center-aligned or must I perform an inversion for the virtual clock and write :

create_clock -name virtual_clock -period $period -waveform {10 20}

And have any idea about the values to constrain in input? Does it depend on the tsu and th of the FPGA?

Thanks again