Interfacing Controller for SDR SDRAM Memory with FPGA Centric Approach

Basically somebody needs to do the 180 degree shift or inversion. If the upstream device is doing it, then:

create_clock -name virtual_clock -period $period -waveform {10 20}

That says there is a 180 degree shift on the virtual clock, which basically means the clock is already aligned in the middle of the data eye at the FPGA pins, and all the FPGA should do is try to match the clock and data delays to the register to maintain that relationship.

The way you have it now, you're saying the clock and data coming from the external device change at the same time(are edge-aligned), which is the worst possible relationship between a clock and data. If this relationship was maintained to the input registers, it would cause a violation. The FPGA will try to add delay to the data path to fix this, but it's not ideal. The way to fix that is:

1) Invert the clock as it feeds the input registers. This centers the clock into the middle of the data eye.

2) Have the PLL port do a 180 degree shift, and make sure the generated clock on the output of the PLL describes it that way(either manually, or with derive_pll_clocks)