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Altera_Forum
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14 years ago

Interfacing Controller for SDR SDRAM Memory with FPGA Centric Approach

Sorry i'm not native english speaker. I'm a begginer in I/Os constraints on Quartus but i've done my best by reading the TimeQuest Timing Analyzer Handbook, other threads , TimeQuest Timing Analyzer ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks for you quick response !

I'm not currently at work. i'll perform the changes tomorrow.

It's not DDR but SDR.

Th requirement of the external device is 1ns so I will change to -1 in set_input_delay, it's my mistake.

On the input side I guess that it's center-aligned because the input clock is inverted with the SDRAM clock and the data from the memory is edge aligned with the SDRAM clock. I don't know if i am clear.