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User1582192733150209's avatar
User1582192733150209
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5 years ago

Intel fft simulation with Modelsim 10.5c starter version /Quartus prime pro 17.1/Aria10gx

Hello Sir/Madam, Quartus prime pro 17.1 + Modelsim 10.5c +Arria10gx I generated an Intel FFT ipcore from Quartus, I can see some files have been generated under the tfft_17_1_0_240_restored\ft\sim\...
User1582192733150209's avatar
User1582192733150209
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi ShYanYewT,

Thanks for your support.

With your suggestion ,I go back to IP setting page and click menu generate->Generate testbench system ,and then

a testbench generation GUI came out , I choosed standard BFM , Verilog MODEL, and output directory is E:/work/fft_new/myfft_tb/

and then click button generate, I can see many files been generated under my nominated location .

I can find the E:\work\fft_new\myfft_tb\myfft_tb\sim\myfft_tb.v , which is the file I mentioned early in last question.

And then start Modelsim-Intel modelsim 10.5c and change directory to

E:\work\fft_new\myfft_tb\myfft_tb\sim\mentor

1,source tcl msim_setup.tcl

2, ld

3, manually add top level signals of testbench into waves window , before this step was done by auto-generated tcl ,

4,run –a

5,check the waveform, I can see the clk and rest_n are working as I expected, but BFM part is not working for some reason.

I have not modify any generated files, all of them are generated by tcl.

Id can be performed successfully ,which means device library and ip library have no issue to be compile.

Is there anything wrong? Or I missed out some steps?

I attached 3 picturs anf my project QAR for reference.

Any suggestion is welcome

thanks

Jim