Forum Discussion
New ContributorIntegration with DSP Builder
Hello,
I am building a PI-controller for an FPGA with the Intel DSP Builder Advanced Blockset. Therefore, I use the forward/backward Euler approach.
I have not enough insights yet in the different clock frequencies and sampling times. What value is used for the sampling time T_s?
I suppose it is not the Clock Frequency in the FPGA. What is it else?
Is there any other possibility to implement an integrator with DSP Builder Blocksets?
Thank you for your support
5 Replies
FvMSuper Contributor
Hello,
T_s isn't a sampling time, it's a factor. Because the integrator input value is added to the integrator once per clock cycle, the factor is scaled with clock frequency.
seb_Thank you. Yeah I understand that T_s is a factor. But is in my example T_s=1/integrator_dspa_param.ClockRate*1e-6? (1e-6 because the clockrate is in MHz)
I am confused because during simulation, it sometimes depends on the simulink step size
- FvMHello,
hardware-wise, time discrete integrator has clearly defined behaviour. 1/z is a single clock cycle delay, e.g. 1 us with 1 MHz clock. Question is if it's correctly modelled in your simulation? I would expect a fixed time step.
Regards
Frank
Kshitij_IntelFrequent Contributor
Hi,
Can you please explore the example design available for PI Controller. Sharing the link below. Yes, PI controller can be designed using dsp builder.
Thank you
Kshitij Goel
- Kshitij_Intel
Hi,
As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Thank you
Kshitij Goel
