Forum Discussion
seb_
New Contributor
New ContributorIntegration with DSP Builder
Hello, I am building a PI-controller for an FPGA with the Intel DSP Builder Advanced Blockset. Therefore, I use the forward/backward Euler approach. I have not enough insights yet in the diff...
FvM
Super Contributor
Super ContributorHello,
T_s isn't a sampling time, it's a factor. Because the integrator input value is added to the integrator once per clock cycle, the factor is scaled with clock frequency.
T_s isn't a sampling time, it's a factor. Because the integrator input value is added to the integrator once per clock cycle, the factor is scaled with clock frequency.
seb_Thank you. Yeah I understand that T_s is a factor. But is in my example T_s=1/integrator_dspa_param.ClockRate*1e-6? (1e-6 because the clockrate is in MHz)
I am confused because during simulation, it sometimes depends on the simulink step size
- FvMHello,
hardware-wise, time discrete integrator has clearly defined behaviour. 1/z is a single clock cycle delay, e.g. 1 us with 1 MHz clock. Question is if it's correctly modelled in your simulation? I would expect a fixed time step.
Regards
Frank
