Honored ContributorHi everyone...
I want ask you a question, In my VHDL design I used integer type as input port and output port, I manage to compile and simulate it using quartus simulator, it goes well. But when I tried to simulate it in ModelSim, I got an error messages like this : "Failure: (vsim-3807) Types do not match between component and entity for port "in_data"." Does anyone know how to solve this problem? Thanks,... :)
Honored ContributorIn the file (second part), you have the following instantiation :
i1 : CounTest
PORT MAP (
-- list connections between master ports and signals
in_clock => in_clock,
in_data => in_data,
in_ena => in_ena,
in_load => in_load,
out_count => out_count
);
SIGNAL in_clock : STD_LOGIC;
SIGNAL in_data : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL in_ena : STD_LOGIC;
SIGNAL in_load : STD_LOGIC;
SIGNAL out_count : STD_LOGIC_VECTOR(4 DOWNTO 0);
Creating testbench require alot of time, so I think use Quartus simulator is best option since I new to FPGA world. :D
Anyway I think by using integer type as port will simplify my design, so I can use it directly in my design, in my code I can increment it by one directly. If I used std_logic_vector it would be difficult.. :D So how is the solution? :)Honored ContributorInteger is not the only one solution. You can use unsigned type. Here is your code modified. Note that you have to include the ieee.numeric_std library to use unsigned.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CounTest is
port (
in_load : in std_logic;
in_data : in std_logic_vector(4 downto 0);
in_clock : in std_logic;
in_ena : in std_logic;
out_count : out std_logic_vector(4 downto 0)
);
end CounTest;
architecture Behavior of CounTest is
signal reg : unsigned(4 downto 0);
begin
process(in_load, in_clock, in_ena)
begin
if (rising_edge(in_clock)) then
if (in_load = '1') then
reg <= unsigned(in_data);
elsif (in_ena = '1') then
reg <= reg + 1;
end if;
end if;
out_count <= std_logic_vector(reg);
end process;
end Behavior;
that is simple code...
More important, the code now can be simulated in ModelSim... Thanks for your solution... I appreciate that... :)Honored ContributorYou're welcome.
