Integer type port

Integer is not the only one solution. You can use unsigned type. Here is your code modified. Note that you have to include the ieee.numeric_std library to use unsigned.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CounTest is
port (
    in_load : in std_logic;
    in_data : in std_logic_vector(4 downto 0);
    in_clock : in std_logic;
    in_ena : in std_logic;
    out_count : out std_logic_vector(4 downto 0)
);
end CounTest;
 
architecture Behavior of CounTest is
    signal reg : unsigned(4 downto 0);
begin
    process(in_load, in_clock, in_ena)
 
    begin
         if (rising_edge(in_clock)) then
              if (in_load = '1') then
                     reg <= unsigned(in_data);
              elsif (in_ena = '1') then
                     reg <= reg +  1;
              end if;
         end if;
         out_count <= std_logic_vector(reg);
     end process;
end Behavior;