Integer type port

In the file (second part), you have the following instantiation :

i1 : CounTest
    PORT MAP (
-- list connections between master ports and signals
    in_clock => in_clock,
    in_data => in_data,
    in_ena => in_ena,
    in_load => in_load,
    out_count => out_count
    );

and just above the declaration of the signals

SIGNAL in_clock : STD_LOGIC;
SIGNAL in_data : STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL in_ena : STD_LOGIC;
SIGNAL in_load : STD_LOGIC;
SIGNAL out_count : STD_LOGIC_VECTOR(4 DOWNTO 0);

You can see that in_data and out_count are defined as std_logic_vector and not integer as you did in your entity, this is why ModelSim gives you the error.

I have never used the Quartus Simulator, but can you explicitely tell it to use integer and not std_logic_vector ?