Honored ContributorI'm setting up an integer signal by saying "signal counter: integer range 0 to 11". To me this means that it would be impossible for me to count higher than 11, but for some reason the counter actually goes up to 15 before wrapping around. Any idea why?
Honored ContributorI am not that familiar with VHDL, but what I suspect is happening is the compiler uses the RANGE value to determine the size of the counter (4 bits), but does not add any logic to start an early wraparound. You probably need to add logic to test for counter == 11 and load the counter with 0 at that point.
Honored ContributorIf I end at 15 and subtract the right amount that I want to count to start at it works. I guess it just has to do with vhdl trying to make its life easier by just going by bits
Honored ContributorHonored ContributorIf you had simulated this before you synthesised it, you would have had the similation throw an out of range error when the integer rolled over passed 11. Integers in VHDL do not roll over.
Like everyone else has said, the synthesiser has converted it to 4 bits and just lets it roll over when it gets to 15. All you have to do to fix this is just do something like this:
process( clk)
begin
if rising_edge(clk) = '1' then
if count = 11 then
count <= 0;
else
count <= count + 1;
end if;
end if;
end process;
