integer doesn't wrap around

If you had simulated this before you synthesised it, you would have had the similation throw an out of range error when the integer rolled over passed 11. Integers in VHDL do not roll over.

Like everyone else has said, the synthesiser has converted it to 4 bits and just lets it roll over when it gets to 15. All you have to do to fix this is just do something like this:

process( clk)
begin
  if rising_edge(clk) = '1' then
    if count = 11 then 
      count <= 0;
    else
      count <= count + 1;
    end if; 
  end if;
end process;

No need to convert it to an unsigned or std_logic_vector - if you mean an integer, then use an integer.