Instantiation of 'stratixii_io' failed. The design unit was not found.---modelsim ero

Hi, I have followed the link http://www.cs.colostate.edu/~cs460/labnotes/modelsimtutorial.html and generated dff_run_msim_rtl.do file in that at end line have attached -L stratixii_ver , then tried to compile.

now I am getting one new error

Error: error deleting "msim_transcript": permission denied

How can I solve the issue?? my Verilog file is a simple dff file. I found the link http://www.alteraforum.com/forum/archive/index.php/t-29390.html giving the solution. but for my Verilog file, I don't knw how it solves the issue??? please reply