Instantiation of DDR3 SDRAM Controller with UniPHY intel FPGA IP

Hi Adzim,

I try to use "External Memory Interface Toolkit" to generate the reports, but there is always an error:

Error occurred while running the System Console command design_link {/designs/ddrc_example.sof} {/devices/5CE(BA5|FA5)@1#USB-1}. System Console returned the result java.util.concurrent.ExecutionException: java.lang.Exception: design_link: Device /devices/5CE(BA5|FA5)@1#USB-1 is not compatible with design /designs/ddrc_example.sof (Design is for 5CGXFC7C7F23C8 but device ID is 02B220DD=5CEBA5/5CEFA5)
invoked from within
"design_link /designs/ddrc_example.sof /devices/5CE(BA5|FA5)@1#USB-1 "
invoked from within
"interp eval $slave {
design_link /designs/ddrc_example.sof /devices/5CE(BA5|FA5)@1#USB-1

}". You must shutdown the toolkit and restart.

I try to reduce JTAG frequency to 6MHz but nothing helped.

With the PLL reference clock frequency setting of 100M, I used oscilloscope to measure the frequency of memory interface clock "MEM_CK" and find the clock is 75M . It seems reasonable, because in our DDR controller configuration, memory clock frequency is : 300MHz, PLL reference clock frequency is 100MHz, rate on avalon_mm interface: full. If the PLL reference clock is given an 25M external clock, the MEM_CK should be 75M (25M * 3 ?)). Isn't it?

Regards,

Scott