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ScottHu2021's avatar
ScottHu2021
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4 years ago

Instantiation of DDR3 SDRAM Controller with UniPHY intel FPGA IP

Dear, We are develop an application with FPGA 5CEFA5F23C8 based on Quartus Prime Standard 18.1. One problem occurred during instantiating DDR3 controller IP core： Our external memory is a DDR3...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Scott,


Every PLL can cover some area of the I/O interfaces.

I think the DDR3 interface can be support at the right side of the Cyclone V device.

So that you need to use the PLL at that area.

But the Quartus can already set for you where by you can see which PLL has been used in the Quartus Compilation Report.


Usually the clock pin is placed in the Address and Command I/O bank.

The clock should be from the Oscillator as you mentioned.


May I see the timing report for DDR?


Thanks,

Adzim


  • ScottHu2021's avatar
    ScottHu2021
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi Adzim,

    In our design, the clock input pin is not placed in the same I/O bank as DDR interface's, and it is used as the PLL reference clock of the DDR3 controller through a clock control block.

    • With the PLL reference clock frequency setting of 100M, the DDR3 can work, and the DDR timing report is as following:

    report_ddr -panel_name "DDR" -multi_corner
    Initializing DDR database for CORE ddrc_p0
    Finding port-to-pin mapping for CORE: ddrc_p0 INSTANCE: ddrc_u|ddrc_inst
    PLL clock ddrc_u|ddrc_inst|pll0|pll1~PLL_OUTPUT_COUNTER|divclk not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Timing analyses may not be valid.
    Report Timing: Found 10 setup paths (0 violated). Worst case slack is 0.048
    Report Timing: Found 10 hold paths (0 violated). Worst case slack is 0.303
    Report Timing: Found 10 recovery paths (0 violated). Worst case slack is 11.589
    Report Timing: Found 10 removal paths (0 violated). Worst case slack is 0.965
    Core: ddrc_p0 - Instance: ddrc_u|ddrc_inst
    setup hold
    Address Command (Slow 1100mV 85C Model) | -0.186 1.878
    Bus Turnaround Time (Slow 1100mV 85C Model) | 4.322 --
    Core (Slow 1100mV 85C Model) | 0.048 0.303
    Core Recovery/Removal (Slow 1100mV 85C Model) | 11.589 0.965
    DQS vs CK (Slow 1100mV 85C Model) | 0.44 0.552
    Postamble (Slow 1100mV 85C Model) | 0.817 0.817
    Read Capture (Slow 1100mV 85C Model) | 0.307 0.26
    Write (Slow 1100mV 85C Model) | 0.633 0.639
    DDR Timing requirements not met

    • With the PLL reference clock frequency setting of 25M, the DDR3 writing/reading failed, and the DDR timing report is as following:

    report_ddr -panel_name "DDR" -multi_corner
    Initializing DDR database for CORE ddrc_p0
    Finding port-to-pin mapping for CORE: ddrc_p0 INSTANCE: ddrc_u|ddrc_inst
    PLL clock ddrc_u|ddrc_inst|pll0|pll1~PLL_OUTPUT_COUNTER|divclk not driven by a dedicated clock pin or neighboring PLL source. To ensure minimum jitter on memory interface clock outputs, the PLL clock source should be a dedicated PLL input clock pin or an output of the neighboring PLL. Timing analyses may not be valid.
    Report Timing: Found 10 setup paths (0 violated). Worst case slack is 1.949

    Report Timing: Found 10 hold paths (0 violated). Worst case slack is 0.303
    Report Timing: Found 10 recovery paths (0 violated). Worst case slack is 11.631
    Report Timing: Found 10 removal paths (0 violated). Worst case slack is 0.838
    Core: ddrc_p0 - Instance: ddrc_u|ddrc_inst
    setup hold
    Address Command (Slow 1100mV 85C Model) | 0.955 0.948
    Bus Turnaround Time (Slow 1100mV 85C Model) | 4.322 --
    Core (Slow 1100mV 85C Model) | 1.949 0.303
    Core Recovery/Removal (Slow 1100mV 85C Model) | 11.631 0.838
    DQS vs CK (Slow 1100mV 85C Model) | 0.44 0.552
    Postamble (Slow 1100mV 85C Model) | 0.817 0.817
    Read Capture (Slow 1100mV 85C Model) | 0.307 0.26
    Write (Slow 1100mV 85C Model) | 0.633 0.639

    Thanks,

    Scott