Forum Discussion

ScottHu2021's avatar
ScottHu2021
Icon for New Contributor rankNew Contributor
4 years ago

Instantiation of DDR3 SDRAM Controller with UniPHY intel FPGA IP

Dear, We are develop an application with FPGA 5CEFA5F23C8 based on Quartus Prime Standard 18.1. One problem occurred during instantiating DDR3 controller IP core： Our external memory is a DDR3...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Scott,


How your PLL ref clock going to drive clock of 100M when the input is 25M?

I think the limitation is depends on the device but I don't know the exact number of it.


Regards,

Adzim


ScottHu2021's avatar
ScottHu2021
Icon for New Contributor rankNew Contributor
4 years ago

Hi Adzim,

one question:

Must the PLL reference clock be from an external clock input (i.e. an oscillator output) and the clock pin must be placed in the same I/O bank as the uniphy's ? （refer to the "External Memory Interface Handbook Volume 3 /Section III. DDR2 and DDR3 SDRAM Controller with UniPHY User Guide: If the PLL input reference clock pin does not have the same I/O standard as the memory interface I/Os, a no-fit might occur because incompatible I/O standards cannot be placed in the same I/O bank.)

Scott