Instantiation of DDR3 SDRAM Controller with UniPHY intel FPGA IP

Hi AdzimZM,

How about the board connection?

=>Sorry, what board connection you mean? BTW, the FPGA used is 5CEFA5F23C8.

Are you using the right clock?

=> In the design, we only have one 25M clock input from external oscillator (the pin assigned is not located the same I/O bank as the uniphy's). And then through a clock control block, the clock is provided to the DDR3 interface input ( pll_ref_clk, as shown above) and to a PLL which derives a 100M clock to drive the other logics.

Is there any timing issue from the Quartus compilation?

=> Yes, only some timing violation issues.

Have you used the 25M setting in the PLL ref clock frequency?

=> If we set the PLL ref clock frequency of the DDR3 controller to 25M, the DDR3 reading/writing can not work. But with 100M setting, the DDR3 works well and also the other logics. The clock summary reported by the Timing Analyzer is as following:

altera_reserved_tck Base 33.333 30.0 MHz 0.000 16.666
clk Generated 10.000 100.0 MHz 0.000 5.000 ==> clk is the output from clock control block, it should be 25M.
clk_in_25M Base 10.000 100.0 MHz 0.000 5.000 ==> input clock from external osicalltor
ddrc_u|ddrc_inst|ddrc_p0_sampling_clock Generated 3.333 300.03 MHz 0.000 1.666
ddrc_u|ddrc_inst|pll0|pll_afi_clk Generated 3.333 300.03 MHz 0.000 1.666
ddrc_u|ddrc_inst|pll0|pll_avl_clk Generated 16.666 60.0 MHz 0.416 8.749
ddrc_u|ddrc_inst|pll0|pll_avl_phy_clk Generated 16.666 60.0 MHz 0.416 8.749
ddrc_u|ddrc_inst|pll0|pll_config_clk Generated 50.000 20.0 MHz 0.000 25.000
ddrc_u|ddrc_inst|pll0|pll_dq_write_clk Generated 3.333 300.03 MHz 2.499 4.165
gpif_clk Base 20.000 50.0 MHz 0.000 10.000
mem_ck[0] Generated 3.333 300.03 MHz 0.000 1.666
mem_ck_n[0] Generated 3.333 300.03 MHz 1.666 3.333
mem_dqs[0]_IN Base 3.333 300.03 MHz 0.000 1.667
mem_dqs[0]_OUT Generated 3.333 300.03 MHz 0.000 1.666
mem_dqs[1]_IN Base 3.333 300.03 MHz 0.000 1.667
mem_dqs[1]_OUT Generated 3.333 300.03 MHz 0.000 1.666
mem_dqs_n[0]_OUT Generated 3.333 300.03 MHz 0.000 1.666
mem_dqs_n[1]_OUT Generated 3.333 300.03 MHz 0.000 1.666

From the reporting, we can see the frequency of the clock "clk" and "clk_in_25M" is not correct.

We defines the base clock and the generated clock in .sdc file as following:

#**************************************************************
# Create Clock
#**************************************************************

create_clock -name {altera_reserved_tck} -period 33.333 -waveform { 0.000 16.666 } [get_ports {altera_reserved_tck}]
create_clock -name {clk_in_25M} -period 40 [get_ports {clk_in_25M}]
create_clock -name {gpif_clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {gpif_pclk}]
create_generated_clock -name clk -source [get_ports {clk_in_25M}] [get_pins {clkin_u|altclkctrl_0|clkin_altclkctrl_0_sub_component|sd1|outclk}]
create_generated_clock -name clk_100m -source [get_pins {clkin_u|altclkctrl_0|clkin_altclkctrl_0_sub_component|sd1|inclk}] -multiply_by 4 [get_pins {clkin_u|altclkctrl_0|clkin_altclkctrl_0_sub_component|sd1|outclk}]
set_clock_groups -logically_exclusive -group [get_clocks {clk_in_25M}] -group [get_clocks {gpif_clk}]

I am not sure if the PLL reference clock must be an external clock input? or can be another DLL output or the output of the clock control block?

Thanks a lot!